added schematics and pcb migrated to kicad 5.0.0 RC2 nightly

This commit is contained in:
Marius K
2018-04-01 17:58:04 +02:00
parent 664545743c
commit fe573aa2cf
41 changed files with 24408 additions and 0 deletions

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(module ZENER_PIN_200MIL (layer F.Cu) (tedit 0)
(descr "<b>Z DIODE</b>")
(fp_text reference Z3 (at -2.6162 -1.524) (layer F.SilkS)
(effects (font (size 1.2065 1.2065) (thickness 0.127)) (justify right top))
)
(fp_text value 3.6V (at -2.54 2.794) (layer F.SilkS)
(effects (font (size 1.2065 1.2065) (thickness 0.127)) (justify right top))
)
(fp_line (start -2.5 -1.15) (end 2.5 -1.15) (layer F.SilkS) (width 0.127))
(fp_line (start 2.5 -1.15) (end 2.5 1.15) (layer F.SilkS) (width 0.127))
(fp_line (start 2.5 1.15) (end -2.5 1.15) (layer F.SilkS) (width 0.127))
(fp_line (start -2.5 1.15) (end -2.5 -1.15) (layer F.SilkS) (width 0.127))
(fp_line (start -0.635 -0.635) (end -0.635 0) (layer F.SilkS) (width 0.127))
(fp_line (start -0.635 0) (end -0.635 0.635) (layer F.SilkS) (width 0.127))
(fp_line (start -0.635 0) (end 0.635 -0.635) (layer F.SilkS) (width 0.127))
(fp_line (start 0.635 -0.635) (end 0.635 0) (layer F.SilkS) (width 0.127))
(fp_line (start 0.635 0) (end 0.635 0.635) (layer F.SilkS) (width 0.127))
(fp_line (start 0.635 0.635) (end -0.635 0) (layer F.SilkS) (width 0.127))
(fp_line (start -0.635 -0.635) (end 0 -0.635) (layer F.SilkS) (width 0.127))
(fp_line (start -0.635 0) (end -1.27 0) (layer F.SilkS) (width 0.127))
(fp_line (start 0.635 0) (end 1.27 0) (layer F.SilkS) (width 0.127))
(fp_line (start -2.6416 -1.3208) (end -2.6416 1.3208) (layer Dwgs.User) (width 0.127))
(fp_line (start -2.6416 1.3208) (end 2.6416 1.3208) (layer Dwgs.User) (width 0.127))
(fp_line (start 2.6416 1.3208) (end 2.6416 -1.3208) (layer Dwgs.User) (width 0.127))
(fp_line (start 2.6416 -1.3208) (end -2.6416 -1.3208) (layer Dwgs.User) (width 0.127))
(pad A thru_hole circle (at 2.54 0) (size 1.6256 1.6256) (drill 0.8128) (layers *.Cu *.Mask)
(solder_mask_margin 0.1016))
(pad K thru_hole rect (at -2.54 0) (size 1.6256 1.6256) (drill 0.8128) (layers *.Cu *.Mask)
(solder_mask_margin 0.1016))
)